Turning to FIG. 1, an example of a conventional serializer/deserializer (SerDes) link 100 can be seen. In operation, the serializer 101 is able to generate a serialized signal for transmission across channel 104 with transmitter 103 (which can include a buffer 102). As a signal x[n] is transmitted across channel 104, an encoding scheme (which has transmit symbols) is employed. An example of an encoding scheme is a 2-level pulse amplitude modulation (2-PAM) scheme (which is referred to as non-return-to-zero or NRZ). For the NRZ scheme, the transmit symbols are −1 and +1. This transmitted signal y[t] is received by the receiver 105. This signal, however, is generally distorted by inter-symbol interference (ISI), so, after the signal is digitized by analog-to-digital converter (ADC) 106, the DFE loop 107 can compensate for the ISI.
In this configuration, the DFE loop 107 is continuously adaptive so as to adjust its feedback to compensate for ISI. To do this, the DFE loop employs an adder 108, comparison circuit 110, and a filter 112 (which is typically a finite impulse response or FIR filter). Generally, the DFE loop 107 (and the filter 112, in particular) uses post-cursor taps to perform this ISI compensation. In FIG. 2, an example of the effective link pulse response can be seen, where h0 is the main cursor and h1 and h2 are post-cursor taps. In this example, samples of the received signal y[t] is as follows:y[n]=h0*x[n]+h1*x[n−1]+h2*x[n−2]+O,  (1)where O is lower order interference (which is ignored in this example). Filter 112 is then able to generate the ISI expression:h1*x[n−1]+h2*x[n−2]  (2)When this ISI expression is subtracted from the signal y[n], the ISI is effectively compensated for. A problem with this configuration is that the speed of the DFE loop 107 is limited by the ability to calculate the ISI expression of equation (2) in one symbol period.
If an NRZ encoding scheme is (for example) employed, the calculations can be approximated. Since signal x[n] can be assumed to be ±1, then the ISI expression of equation (2) can be assumed to be:h1+h2;  (3)h1−h2;  (4)−h1+h2; or  (5)−h1−h2.  (6)Thus, DFE loop 107 can be replaced with DFE loop 203 in receiver 201 of SerDes link 200, as shown in FIG. 3. This is generally referred to as a speculative DFE. In this configuration, compensators 206-1 to 206-4 calculate equations (3) to (6) substantially simultaneously, and comparison results are determined by comparators 204-1 to 204-4. These comparison results are multiplexed by multiplexer or mux 208, where the select signal SELECT is calculated from signals x[n−1] and x[n−2].
The SerDes link 200, shown in FIG. 3, can be expanded so as to be employed with other encoding schemes (such as M-PAM) and with larger numbers of post-cursor taps. Some problems with this speculative DFE configuration, though, are complexity, power consumption, and area usage, which can largely be attributed to the number of comparators. As shown in FIG. 3, four comparators are employed, but for an M-PAM system the number of comparators is MN, where M is the number of transmit symbols and N is the number of taps. For a 4-PAM system having 2 taps and 3 decision levels, there are 16 comparators per decision level and 48 total comparators (as can be seen in example of FIG. 4). Thus, there is a need for an improved DFE.
Some other conventional systems are: U.S. Pat. Nos. 7,539,243; 7,792,187; 7,822,114; U.S. Patent Pre-Grant Publ. No. 2008/0187036; U.S. Patent Pre-Grant Publ. No. 2009/0285277; U.S. Patent Pre-Grant Publ. No. 2009/0304066; U.S. Patent Pre-Grant Publ. No. 2010/0054324; and van Ierssel et al., “An Adaptive 4-PAM Decision-Feedback Equalizer for Chip-to-Chip Signaling,” IEEE Intl. SOC Conf. Proceedings, 2004, Sep. 12-15, 2004, pp. 297-300.